The present invention relates to an input buffer circuit and a logic circuit suitably built in superhigh-speed and high-integration LSI devices used in large scale computers and the like.
As the performance of large scale computers is enhanced, superhigh-speed logic LSI devices used are required to have an increased operating speed, increased density of circuit integration and decreased power consumption per unit circuit. In order to reduce power consumption of a circuit while retaining its fast operating property, lowering the supply voltage becomes a crucial technique.
FIG. 1 shows schematically a conventional input buffer circuit used in LSI devices as disclosed, for example, in Japanese Patent Application Laid-open No. 58-83434. In the figure, reference number 1 denotes an input terminal, 2 is an input protection circuit, and 3 is an output terminal. The circuit operates to receive the input signal with a differential transistor circuit made up of two transistors Q1' and Q2', and provide the in-phase output signal via a transistor Q3' in emitter-follower configuration. The differential transistor circuit is ridded of a threshold by having a feedback of the in-phase output signal to the inverting transistor Q2'.
Generally, fast-operating LSI devices employ ECL (Emitter Coupled Logic) levels as the input and output signal levels. Typical ECL levels range between -0.8 and -0.9 volt as a high level and between -1.6 and -1.8 volts as a low level. On this account, a voltage range approximately from -1.6 to `1.8 volts needs to be assured for a low level voltage. In the circuit arrangement of FIG. 1, if the voltage drop across current source resistor R3' in the differential transistor circuit is made smaller, the variation in the output voltage at the output terminal 3 increases relative to the variation in the input voltage or the supply voltage V.sub.EE ', resulting in a reduction in a marginal operating condition. Therefore, when the circuit of FIG. 1 is designed to receive ECL-level signals, the supply voltage V.sub.EE ', cannot be made smaller than -3 volts on assumption that the variation of V.sub.EE ', is around .+-.10%. Accordingly, it is limited to reduce the power consumption of a circuit by decreasing the supply voltage.
FIG. 2 shows another conventional circuit arrangement disclosed in U.S. Pat. No. 3,795,822. In the figure, reference numbers 100 and 101 denote input terminals and 200 and 201 denote output terminals. The arrangement includes an input multiemitter transistor Q2", an output multiemitter transistor Q3", a clamping transistor Q9" terminating resistors R100 and R101, and a load resistor R102 for the input transistor Q2". The circuit operates under a negative supply voltage V.sub.EE ". The above circuit arrangement is used primarily as a logic gate circuit, but its basic configuration is also capable of use as an input buffer circuit for LSI devices. The circuit receives input signals directly at multiple emitters of the input transistor Q2", and can operate under a smaller supply voltage condition V.sub.EE " than the conventional case shown in FIG. 1 by the amount equal to the base-to-emitter voltage V.sub.BE of the input transistor Q1'. A low output level at the output terminal 200 or 201 varies in response to the variation in the negative supply voltage V.sub.EE ", and the output variation is equal to the supply voltage variation multiplied by the ratio of a voltage drop across the terminating resistor R100 (R101) to a voltage drop across the load resistor R102. Accordingly, decreasing the negative supply voltage V.sub.EE " causes a falling voltage drop across the terminating resistor R100 (R101), which results in an increased output variation and, thus, in narrower marginal operating condition of the circuit.
Suppose that the circuit of FIG. 2 receives an ECL-level signal, i.e., the circuit is designed to produce a signal amplitude of about 500 mV at the output terminal 200 (201) under a supply voltage variation of .+-.10%. For the negative supply voltage V.sub.EE " having a center value of -2.5 volts, the variation in a low output at the output terminal 200 (201) will be approximately .+-.150 mV. Actually, the input signal applied to the input terminal 100 (101) also varies, and therefore the negative supply voltage V.sub.EE " for the input buffer circuit of this arrangement will have a practical upper limit lower than -2.5 volts. The smaller the absolute value of the negative supply voltage, the more reduction in the power consumption of the circuit is possible. However, because of its adverse effect on the low output level variation, reduction in the absolute value of the negative supply voltage is limited.